1. Technical Field
The present general inventive concept relates to semiconductor memory devices such as dynamic random access memories (DRAMs) and, more particularly, to a refresh circuit in a semiconductor memory device which is capable of minimizing and reducing peak current during a refresh operation.
2. Discussion of the Related Art
Semiconductor memory devices such as DRAMs are widely used as main memories in electronic devices such as computers. Semiconductor memory devices are made of a semiconductor material such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP). Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.
DRAMs are volatile semiconductor memories which lose their stored data when their power supplies are interrupted. Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two logic values of a bit, conventionally called “0” and “1”. Since capacitors leak charge, DRAMs require a periodic refresh operation for reading data already stored in a memory cell and then restoring (re-writing) the read data to the same memory cell.
While being similar to a data read operation, a refresh operation of a DRAM is different from the data read operation in that data is generally not output to an external host processor (e.g., a CPU).
Typically, designer specify that each row must have its storage cell capacitors refreshed every 64 ms or less, as defined by the JEDEC (Foundation for developing Semiconductor Standards) standard. Refresh logic is provided in a DRAM controller which automates the periodic refresh. In general, a refresh operation of a DRAM is performed by applying a row address strobe (RASB) signal to the DRAM after a high-to-low transition of the RASB signal, activating a wordline corresponding to a row address to be refreshed, and driving a bitline sense amplifier for sensing the existing (already stored) data in the memory cell.
Typically, manufacturers specify that each row must have its storage cell capacitors refreshed every 64 ms or less, as defined by the JEDEC (Foundation for developing Semiconductor Standards) standard. Refresh logic is provided in a DRAM controller which automates the periodic refresh, that is no software or other hardware has to perform it. This makes the controller's logic circuit more complicated, but this drawback is outweighed by the fact that DRAM is much cheaper per storage cell and because each storage cell is very simple, DRAM has much greater capacity per geographic area than SRAM.
Some systems refresh every row in a burst of activity involving all rows every 64 ms. Thus, the self-refresh operation period is 64 ms. Other systems refresh one row at a time throughout the 64 ms interval. For example, a system with 8192 rows would require a refresh rate of one row every 7.8 μs which is 64 ms divided by 8192 rows. A few real-time systems refresh a portion of memory at a time determined by an external timer function that governs the operation of the rest of a system, such as the vertical blanking interval that occurs every 10-20 ms in video equipment. All methods require some sort of counter to keep track of which row is the next to be refreshed.
A conventional refresh standard of a DRAM is 16 ms/1024(cycle) in 4 megabytes. Thus, it has been recommended to maintain a refresh interval of 15.6 microseconds. Since the refresh time should be the same despite any increase in memory density of a DRAM, various methods have been studied to decrease the number of refresh cycles. These method are not to execute refresh cycles of the same number as rows (as in less dense DRAMS) but to increase the number of rows activated during a refresh operation. For example, if row activation is conducted by one-eighth (of rows) when a semiconductor memory device performs a normal operation, row activation is conducted by a quarter or half (of rows) in case of a refresh operation. Thus, the number of rows activated during the refresh operation increases two or four times as large as in case of the normal operation and thus the number of refresh cycles decreases.
However, an increase of row activation during the refresh operation causes the disadvantage that since the number of concurrently operating memory portions increases, a noise peak value increases.
And, if the number of rows activated at a time increases so as to decrease the number of refresh cycles during a refresh operation of a DRAM, it is difficult to minimize or reduce peak current.